How CPUs Work: Transistors, Clock Cycles, and Modern Processor Design

The Transistor: Smallest Switch in the Universe

Every computation your computer performs ultimately reduces to billions of transistors switching between on and off states billions of times per second. A transistor is a semiconductor device that acts as an electrically controlled switch: a small voltage applied to one terminal (the gate) controls whether current can flow between the other two terminals (source and drain). When the gate voltage is above a threshold, the transistor is on (current flows); below the threshold, it is off (current blocked). These binary states correspond to the 1s and 0s of digital logic, and by combining transistors into logic gates — AND, OR, NOT, NAND, NOR, XOR — engineers can build circuits that perform any logical or arithmetic operation imaginable.

Modern CPUs contain tens of billions of transistors etched onto a piece of silicon roughly the size of a fingernail. The 2 nanometer manufacturing process nodes from leading chipmakers like TSMC and Samsung pack transistors so tightly that thousands of them could fit across a single human hair. Achieving this density requires extreme ultraviolet (EUV) lithography — a technology that uses 13.5 nm wavelength light generated by superheated tin plasma to project circuit patterns onto silicon wafers with atomic-scale precision. The manufacturing process involves hundreds of sequential steps of deposition, patterning, etching, and doping across a wafer that may be 300 millimeters in diameter, producing hundreds of individual chips simultaneously.

The metal-oxide-semiconductor field-effect transistor (MOSFET) is the transistor type used in virtually all modern CPUs. As transistors have shrunk toward atomic dimensions, their behavior has become increasingly quantum mechanical, with electrons tunneling through barriers that classical physics says they should not be able to cross. Chipmakers have responded with architectural innovations — FinFET transistors that surround the channel with a three-dimensional gate fin, and Gate-All-Around (GAA) nanosheet transistors that wrap the gate completely around the channel — to maintain control of electron flow as dimensions shrink.

Logic Gates to Arithmetic: Building Blocks of Computation

Combining transistors into logic gates and logic gates into functional units yields the building blocks of a processor. An adder circuit, built from a tree of XOR and AND gates, can add two binary numbers together in a handful of nanoseconds. More complex circuits — multipliers, dividers, shift registers, comparators — perform the arithmetic and logical operations that CPUs execute. The Arithmetic Logic Unit (ALU) is the CPU functional unit that performs integer arithmetic and bitwise logical operations, and every CPU contains one or more ALUs at its computational core.

Floating-point operations — arithmetic on numbers with decimal points, essential for graphics, scientific computing, and machine learning — are handled by the Floating Point Unit (FPU). Modern CPUs also include vector processing units that can perform the same operation on multiple data items simultaneously — a paradigm called SIMD (Single Instruction, Multiple Data). Intel's AVX-512 extension, for example, can process 512 bits of data in a single instruction, performing operations on sixteen 32-bit floating-point numbers simultaneously — a massive throughput advantage for heavily vectorizable workloads like signal processing and neural network inference.

The Instruction Cycle: Fetch, Decode, Execute

At the most fundamental level, a CPU operates by repeatedly executing the fetch-decode-execute cycle. In the fetch stage, the CPU reads the next instruction from memory, using the Program Counter (PC) register to know where to look. In the decode stage, the Control Unit interprets the instruction's binary encoding to determine what operation to perform and which registers or memory locations contain the operands. In the execute stage, the appropriate functional unit (ALU, FPU, memory access unit) performs the operation and writes the result to a register or memory location. The PC then advances to the next instruction and the cycle repeats.

Early CPUs executed one instruction per cycle, making each stage sequential. Modern out-of-order superscalar processors can execute many instructions simultaneously, achieving instruction-level parallelism through several key mechanisms. Pipelining divides instruction execution into multiple stages (typically 10 to 20 in modern CPUs) so that different instructions can occupy different stages simultaneously — like an assembly line where each worker performs one step of a product's assembly while the next product enters the line. Superscalar execution replicates functional units so that multiple instructions at the same pipeline stage can proceed in parallel if they are independent. Out-of-order execution allows the processor to reorder instructions and execute them as soon as their operands are available, even if they appear later in the instruction stream than instructions that are waiting for data — a technique that dramatically increases utilization of execution units.

Caches: Bridging the Speed Gap Between CPU and RAM

Modern CPUs can execute instructions in fractions of a nanosecond, but main memory (DRAM) takes 50 to 100 nanoseconds to respond to a request — a factor of 100 to 200 slower. If the CPU had to wait for main memory on every instruction, most of its time would be spent idle. The solution is a hierarchy of small, fast cache memories built directly on the processor die, holding recently and frequently accessed data and instructions.

Level 1 (L1) cache is the smallest and fastest — typically 32 to 64 kilobytes per core — and responds in 4 to 5 clock cycles. Level 2 (L2) cache is larger (256 KB to 1 MB per core) and slightly slower (10 to 15 cycles). Level 3 (L3) cache is shared among cores — ranging from 4 MB to over 100 MB in high-end server processors — and takes 30 to 50 cycles to access but avoids the full trip to DRAM. When the CPU requests data, hardware checks each cache level in order; a hit delivers the data quickly, while a miss forces retrieval from the next slower level. Cache hit rates of 95 percent or higher are typical for well-behaved programs, dramatically reducing effective memory latency. Cache coherence protocols ensure that when multiple cores each have a copy of the same memory location in their private caches, updates by one core are reflected correctly in others — a complex distributed systems problem solved by protocols like MESI (Modified, Exclusive, Shared, Invalid).

Multiple Cores and Modern CPU Architecture

For most of computing history, CPU performance improved primarily by increasing clock frequency — the number of instruction cycles per second. Clock speeds rose from megahertz in the 1980s to over 3 GHz by the early 2000s. But at that point, power consumption and heat dissipation became limiting factors: doubling frequency quadruples dynamic power consumption (power scales with frequency and with voltage squared). The industry response was to shift to multicore processors — placing multiple complete CPU cores on a single die, each running at a moderate clock speed but collectively delivering far higher throughput for parallel workloads.

Modern desktop processors commonly feature 8 to 24 cores; server processors for data centers reach 64 to 128 cores on a single chip. Intel's hybrid architecture, used in recent Core processors, combines performance cores (P-cores) optimized for single-threaded speed with efficiency cores (E-cores) optimized for power-efficient throughput, assigning tasks intelligently based on their priority and parallelism. AMD's chiplet approach assembles processors from multiple smaller dies (chiplets) manufactured separately and interconnected by a high-bandwidth die-to-die bus, allowing yields and flexibility that monolithic dies of equivalent area could not achieve economically.

Branch Prediction, Speculation, and Security

Conditional branches — if/else statements in code — pose a fundamental challenge for pipelined processors. When the CPU encounters a branch instruction, it does not know until it evaluates the condition whether to continue executing the sequential instruction stream or jump to a different location. If the pipeline simply stalls to wait for the branch result, 10 to 20 pipeline stages sit idle — devastating performance. The solution is branch prediction: dedicated hardware that predicts which path will be taken based on historical patterns, speculatively executing instructions along the predicted path before the branch resolves. Modern branch predictors achieve accuracy rates above 95 percent, filling pipelines productively. When a misprediction is detected, the speculatively executed instructions are discarded and execution restarts on the correct path — wasting some cycles but still far better than always stalling.

Speculative execution and the memory hierarchy interact in ways that created a class of serious security vulnerabilities discovered in 2018 and named Spectre and Meltdown. These attacks exploit the fact that speculatively executed instructions leave traces in cache state even when their results are discarded, allowing a carefully crafted program to infer the contents of memory it should not be able to access. Mitigating these vulnerabilities required changes to both hardware design and operating system code, and managing the security implications of speculative execution remains an active area of processor architecture research. The history of these vulnerabilities illustrates a broader truth about computing: the cleverer the optimization, the more subtle and unexpected its interactions with the rest of the system can be.