How Semiconductors Are Manufactured at the Nanometer Scale

A Modern Chip Contains More Transistors Than There Are Stars in the Milky Way

Apple's M3 Ultra chip, released in 2024, contains 192 billion transistors on a die area of 1,330 mm² — roughly the size of a large postage stamp. The Milky Way galaxy contains an estimated 200–400 billion stars. These transistors are fabricated using 3 nm process nodes, where individual features are smaller than some protein molecules. The precision required makes semiconductor manufacturing arguably the most technically demanding industrial process humanity has ever developed.

Semiconductors are materials whose electrical conductivity falls between conductors and insulators. Silicon dominates the industry because of its abundance, its native oxide (SiO₂) which makes an excellent electrical insulator, and decades of accumulated process knowledge. Every transistor on a chip is essentially a voltage-controlled switch: apply voltage to the gate, and current flows between source and drain. Pack billions of these switches per square centimeter and you have a modern processor.

The Silicon Wafer: Starting Point

The process begins with hyperpure silicon — 99.9999999% (nine nines) pure. Metallurgical-grade silicon from quartz sand is purified by conversion to trichlorosilane gas, then deposition in the Siemens process. The resulting polysilicon is melted and grown into a single-crystal cylindrical ingot (a boule) using the Czochralski method: a seed crystal is dipped into a 1,414°C silicon melt and slowly pulled upward while rotating.

The boule — typically 300 mm diameter for logic chips — is sliced into wafers 775 µm thick, polished to atomic-level flatness, and cleaned. This single wafer becomes the substrate for hundreds of individual chips processed simultaneously.

Photolithography: Printing Circuits with Light

Photolithography is the core patterning process. A photosensitive material called photoresist is spin-coated onto the wafer. Light is projected through a reticle (mask) containing the circuit pattern, exposing the resist. Chemical development removes either exposed or unexposed resist, leaving behind a pattern that protects selected areas during subsequent etching or deposition steps.

Resolution in photolithography is governed by the Rayleigh criterion: R = k₁ × λ/NA, where λ is the wavelength of light, NA is the numerical aperture of the lens, and k₁ is a process-dependent constant (theoretically as low as 0.25). Shrinking features requires shorter wavelengths, higher NA, or lower k₁.

EUV Lithography: The $200 Million Machine

Extreme ultraviolet lithography uses 13.5 nm wavelength light — in the soft X-ray range — to print features below 7 nm. This technology required three decades of development and represents one of the most complex machines ever built. ASML, the Dutch company with a near-monopoly on EUV equipment, produces approximately 50 EUV systems per year at roughly $200 million each.

EUV light is generated by firing 50,000 laser pulses per second at tin droplets 30 µm in diameter, converting them to plasma that emits 13.5 nm light. Conventional glass lenses absorb EUV — mirrors coated with alternating layers of silicon and molybdenum are used instead, each reflecting roughly 68% of incident light. The entire optical path must be in a near-perfect vacuum, as air absorbs EUV. The machine must position the wafer with sub-nanometer accuracy while the stage moves at meters per second.

Doping: Tuning Silicon's Electrical Properties

Undoped silicon conducts poorly. Controlled introduction of impurities (dopants) at concentrations of one part per billion to one part per million transforms its electrical behavior.

• n-type doping: Introducing phosphorus or arsenic atoms (Group V) adds free electrons — negative charge carriers. Transistor regions requiring electron flow are n-doped.
• p-type doping: Boron or gallium atoms (Group III) create "holes" — effectively positive charge carriers. Transistor regions requiring hole flow are p-doped.
• Ion implantation: Dopant atoms are ionized and accelerated to energies of 10–500 keV, driven precisely into the silicon to exact depths. Annealing then activates the dopants electrically.

The Full Process: 500 Steps Over Three Months

A complete chip fabrication cycle involves 500–1,000 individual process steps and takes 10–14 weeks. The major categories:

• Oxidation: Thermal oxidation grows SiO₂ gate dielectric layers, now replaced by high-k dielectrics (HfO₂) at advanced nodes.
• Deposition: Chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD) build up thin film layers — metals, insulators, semiconductors.
• Etching: Plasma etching removes material with atomic precision. Reactive ion etching (RIE) achieves aspect ratios (depth-to-width) of 10:1 or more.
• Planarization: Chemical mechanical polishing (CMP) uses a slurry of abrasive particles and chemicals to flatten surfaces to sub-nanometer roughness — essential for stacking multiple metal interconnect layers.
• Interconnects: Up to 15 layers of copper metal lines (the "back end of line") connect transistors into circuits.

Yield: The Economics of Imperfection

No wafer is manufactured perfectly. Random defects — particles, crystal dislocations, process variations — kill some fraction of chips on every wafer. Yield — the percentage of functional chips per wafer — determines manufacturing economics.

For leading-edge nodes at early production stages, yields below 50% are typical. Mature processes achieve 95%+. A single particle of dust during lithography can ruin an entire chip. Semiconductor cleanrooms are classified to ISO 1 or ISO 2 standards — at ISO 1, the cleanroom contains fewer than 10 particles larger than 0.1 µm per cubic meter. Outside air contains approximately 35 million particles per cubic meter. Workers wear full body suits and breathe filtered air to avoid contaminating the environment.

The Limits Ahead

Progress beyond 2 nm faces fundamental physical barriers. Gate lengths approaching 1 nm — a few silicon atoms wide — suffer from quantum tunneling: electrons pass through the gate barrier regardless of the voltage applied, causing leakage current. The industry is responding with novel transistor architectures (gate-all-around nanosheets replacing finFETs), new channel materials (strained silicon, gallium arsenide), 3D chip stacking, and chiplet integration that assembles multiple dies in a single package. The manufacturing challenge for the next decade is no longer simply shrinking transistors but innovating the entire architecture of how chips are built and connected.