How Memory Chips Store and Retrieve Information

A Trillion-Dollar Industry Built on Trapped Electrons

The global semiconductor memory market reached approximately $118 billion in 2023, dominated by three companies—Samsung, SK Hynix, and Micron—that collectively produce the vast majority of the world's DRAM and NAND flash storage. Every smartphone, laptop, server, and solid-state drive relies on chips that store data as electrical charge in structures measured in nanometers. Modern NAND flash stores 3 bits of data per cell in a volume smaller than a virus. The engineering required to achieve this—and to read those bits back reliably billions of times—sits at the frontier of what physics allows.

DRAM: Fast but Forgetful

Dynamic Random Access Memory (DRAM) is the working memory of computers—the RAM in your phone and laptop. Each bit of data in DRAM is stored in a cell consisting of one transistor and one capacitor. The capacitor holds charge (representing 1) or lacks charge (representing 0). The transistor acts as a gate, controlling access to the capacitor for reading and writing.

DRAM is fast—modern DDR5 (Double Data Rate 5) RAM operates at 4,800–8,400 MHz with read latencies of approximately 10–14 nanoseconds. But it is "dynamic" because capacitors leak charge over time. Without periodic refresh cycles (typically every 64 milliseconds), stored data disappears. This constant refreshing consumes power and limits density improvement. DRAM is also volatile: cut power, and all data is lost instantly. A typical modern DRAM cell area is approximately 6F² (where F is the minimum feature size), and leading DRAM nodes from Samsung and SK Hynix have reached below 14 nm feature sizes.

ECC (Error-Correcting Code) DRAM, used in servers, adds extra memory cells to detect and correct single-bit errors that occur due to cosmic ray bit flips or cell leakage. In large-scale data centers running millions of DRAM cells, uncorrected memory errors would cause frequent server crashes.

NAND Flash: Persistent but Physically Finite

NAND flash memory stores data in floating-gate transistors or, in newer designs, charge-trap transistors. The floating gate is a layer of polysilicon completely surrounded by insulating oxide, electrically isolated from the rest of the transistor. Charge (electrons) is injected onto the floating gate by quantum mechanical tunneling through the thin oxide layer using high voltage (~15–20V in programming). Once stored, the charge alters the transistor's threshold voltage—the voltage required to switch it on—which can be measured to read the stored data.

The trade-off is fundamental: more bits per cell requires distinguishing more voltage levels, demanding tighter manufacturing tolerances, causing more read/write errors, and reducing the number of program/erase cycles before cells wear out. Each P/E cycle slightly degrades the oxide insulator; after enough cycles, charge retention fails.

SSDs vs. HDDs: Different Physics, Different Trade-offs

Solid-state drives (SSDs) package NAND flash with a controller chip that manages wear leveling (distributing writes across cells to prevent premature wear), error correction, and the flash translation layer (FTL) that maps logical addresses to physical NAND locations. Hard disk drives (HDDs) store data magnetically on spinning platters using read/write heads that physically move to access different tracks.

• Read speed: NVMe SSD (7,000+ MB/s sequential) vs. HDD (200–300 MB/s) — SSDs win by 20–30×
• Random access latency: SSD (~100 microseconds) vs. HDD (~5–10 milliseconds) — SSDs win by 50–100×
• Cost per terabyte (2024): SSD (~$60–90/TB) vs. HDD (~$20–30/TB) — HDDs win by 3–4×
• Capacity: HDDs reach 22+ TB in single drives; NAS-oriented HDDs scale to 30+ TB (HAMR technology from Seagate)
• Durability: SSDs have no moving parts; HDDs are vulnerable to shock and vibration

HDDs remain dominant for bulk cold storage precisely because they are cheaper per terabyte and retain excellent longevity for sequential read/write workloads. SSDs dominate system drives, where access speed transforms the user experience.

Moore's Law and the 3D NAND Solution

Gordon Moore's 1965 observation—that transistor density on a chip doubles approximately every two years—guided semiconductor industry roadmaps for six decades. But for NAND flash, continued 2D (planar) shrinking hit a fundamental limit around 2013–2015: as cells shrank below 15–20 nm, floating gates were physically so close together that stored charge bled between adjacent cells, making reliable multi-bit storage impossible.

The industry's solution was to stop shrinking in 2D and start building up in 3D. Samsung introduced the first commercial 3D NAND (V-NAND) in 2013, stacking 24 layers of NAND cells vertically. By 2024, leading manufacturers ship NAND with 200+ layers:

• Samsung: 290+ layer V-NAND (2024)
• SK Hynix: 238 layer (2023), 321 layer in development
• Micron: 232 layer (2022)
• Kioxia/WD: 218 layer (2023)

3D NAND uses slightly larger cell feature sizes than planar NAND's final generations, improving reliability and endurance per layer while achieving higher total density through stacking. A single 3D NAND die from a modern manufacturer contains hundreds of billions of cells in a chip the size of a fingernail.

The Physics Walls Ahead

Memory density scaling faces genuine physical limits. For DRAM, continued capacitor miniaturization is extraordinarily difficult—capacitors must store enough charge to be reliably read above the noise floor, limiting how small they can shrink. Chipmakers are turning to buried word-line structures and new dielectric materials (high-κ materials like hafnium oxide) to maintain capacitance in smaller cells.

For NAND, stacking more layers requires deeper etching of word-line channels through increasingly thick material stacks—an engineering challenge where process control at nanometer scale becomes nearly impossible beyond certain heights. Some manufacturers are pursuing bonded-wafer approaches (stacking separately fabricated dies) rather than single-stack etching.

Emerging memory technologies—3D XPoint/Optane (Intel/Micron, now discontinued commercially), MRAM (magnetic RAM, now produced by Everspin and Samsung), RRAM/ReRAM, and FeRAM—offer different trade-offs in speed, endurance, and density that may fill gaps as DRAM and NAND scaling slows. The electrons keep finding new ways to carry information.